Design of cortically implanted neural prosthetic sensors (CINPS) is an active area of research in the rapidly emerging field of brain machine interfaces (BMI). The core technology of these sensors is micro-electrode arrays that facilitate real-time recording from thousands of neurons simultaneously. These recordings are then actively processed at the sensor and transmitted to an off-scalp neural processor which controls the movement of a prosthetic limb. A key challenge in designing implantable integrated circuits (IC) for CINPS is to efficiently process high-dimensional signals generated at the interface of micro-electrode arrays. Sensor arrays consisting of more than 1000 recording elements are common which significantly increase the transmission rate at the sensor. A simple strategy of recording, parallel data conversion and transmitting the recorded neural signals (at a sampling rate of 10 KHz) can easily exceed the power dissipation limit of 80 mW/cm2 determined by local heating of biological tissue. In addition to increased power dissipation, high-transmission rate also adversely affects the real-time control of neural prosthesis.
One of the solutions that have been proposed by several researchers is to perform compression of the neural signals directly at the sensor, to reduce its wireless transmission rate and hence its power dissipation. Currently most compression strategies are performed subsequent to an analog-to-digital conversion stage. This disclosure presents an approach where de-correlation or redundancy elimination is performed directly at analog-to-digital converter. It has been shown that neural cross-talk and common-mode effects introduce unwanted redundancy at the output of the electrode array. As a result neural signals typically occupy only a small sub-space of the high-dimensional space spanned by the micro-electrode signals. An optimal strategy for designing a multi-channel analog-to-digital converter is to identify and operate within the subspace spanned by the neural signals and in the process eliminate cross-channel redundancy and perform spatial compression. To achieve this goal, this disclosure proposes to use large margin principles, which have been highly successful in high-dimensional information processing. This approach will be to formalize a cost function consisting of L1 norm of the internal state vector whose gradient updates naturally lends to a digital time-series expansion. Within this framework the correlation distance between the channels will be minimized which amounts to searching for signal spaces that are maximally separated from each other. The architecture called multiple-input multiple-output (MIMO) sigma-delta (ΣΔ) converter is the first reported data conversion technique to embed large margin principles. The approach, however, is generic and can be extended to designing higher order analog-to-digital converters. The statements in this section merely provide background information related to the present disclosure and may not constitute prior art.